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SEMICONDUCTOR TECHNICAL DATA
Freescale Semiconductor, Inc. Document Number: MPC9893/D Rev 3, 01/2004
Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch
The MPC9893 is a 2.5V and 3.3V compatible, PLL based intelligent dynamic clock switch and generator specifically designed for redundant clock distribution systems. The device receives two LVCMOS clock signals and generates 12 phase aligned output clocks. The MPC9893 is able to detect a failing reference clock signal and to dynamically switch to a redundant clock signal. The switch from the failing clock to the redundant clock occurs without interruption of the output clock signal (output clock slews to alignment). The phase bump typically caused by a clock failure is eliminated. The device offers 12 low skew clock outputs organized into two output banks, each configurable to support the different clock frequencies. The extended temperature range of the MPC9893 supports telecommunication and networking requirements. The device employs a fully differential PLL design to minimize jitter. Features * 12 output LVCMOS PLL clock generator
MPC9893
LOW VOLTAGE 2.5V AND 3.3V IDCS AND PLL CLOCK GENERATOR
Freescale Semiconductor, Inc...
* * * * * * * * * * * *
2.5V and 3.3V compatible IDCS - on-chip intelligent dynamic clock switch Automatically detects clock failure Smooth output phase transition during clock failover switch 7.5 - 200 MHz output frequency range LVCMOS compatible inputs and outputs External feedback enables zero-delay configurations Supports networking, telecommunications and computer applications Output enable/disable and static test mode (PLL bypass) Low skew characteristics: maximum 50 ps output-to-output (within bank) 48 lead LQFP package Ambient operating temperature range of --40 to 85C
FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932
Functional Description The MPC9893 is a 3.3V or 2.5V compatible PLL clock driver and clock generator. The clock generator uses a fully integrated PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by one, two, three, four or eight. The frequency-multiplied clock drives six bank A outputs. Six bank B outputs can run at either the same frequency than bank A or at half of the bank A frequency. Therefore, bank B outputs additionally support the frequency multiplication of the input reference clock by 3/2 and 1/2. Bank A and bank B outputs are phase-aligned1. Due to the external PLL feedback, the clock signals of both output banks are also phase-aligned1 to the selected input reference clock, providing virtually zero-delay capability. The integrated IDCS continuously monitors both clock inputs and indicates a clock failure individually for each clock input. When a false clock signal is detected, the MPC9893 switches to the redundant clock input, forcing the PLL to slowly slew to alignment and not produce any phase bumps at the outputs. Both clock inputs are interchangeable, also supporting the switch to a failed clock that was restored. The MPC9893 also provides a manual mode that allows for user-controlled clock switches. The PLL bypass of the MPC9893 disables the IDCS and PLL-related specifications do not apply. In PLL bypass mode, the MPC9893 is fully static in order to distribute low-frequency clocks for system test and diagnosis. Outputs of the MPC9893 can be disabled (high-impedance tristate) to isolate the device from the system. Applying output disable also resets the MPC9893. On power-up this reset function needs to be applied for correct operation of the circuitry. Please see the application section for power-on sequence recommendations. The device is packaged in a 7x7 mm2 48-lead LQFP package.
1. At coincident rising edges
(c) Motorola, Inc. 2004
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MPC9893
Freescale Semiconductor, Inc.
QA0
CLK0 CLK1 FB REF_SEL MAN/A ALARM_RST
(pulldown) (pulldown) (pulldown)
0 Ref 1
0 1 D Q
QA1 QA2 QA3 QA4
PLL 240 - 400 MHz
FB
IDCS
(pulldown) (pullup) (pullup)
QA5 QB0 QB1
D Q
QB2 QB3
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PLL_EN FSEL[0:3]
(pulldown) (pulldown)
QB4 QB5 Data Generator
D Q
QFB ALARM0 ALARM1 CLK_IND
OE/MR
(pulldown)
Figure 1. MPC9893 Logic Diagram
ALARM_RST REF_SEL PLL_EN
FSEL0
FSEL1
FSEL2
FSEL3
GND
GND
VCC
GND QA0 QA1 VCC GND QA2 QA3 VCC GND QA4 QA5 VCC
37 38 39 40 41 42 43 44 45 46 47 48
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1 2 QFB 3 FB 4 MAN/A 5 VCC 6 CLK0 7 CLK1 8 VCC_PLL 13 9 10 11 12 CLK_IND ALARM0 ALARM1 GND
VCC
OE
GND QB0 QB1 VCC GND QB2 QB3 VCC GND QB4 QB5 VCC
MPC9893
It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see application section for details.
Figure 2. 48-Lead Package Pinout (Top View)
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GND
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Table 1: PIN CONFIGURATION
Pin CLK0, CLK1 FB REF_SEL MAN/A ALARM_RST PLL_EN FSEL[0:3] OE/MR QA[0:5] QB[0:5] QFB ALARM0 ALARM1 CLK_IND GND VCC_PLL Input Input Input Input Input Input Input Input Output Output Output Output Output Output Supply Supply I/O Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC PLL reference clock inputs PLL feedback signal input, connect directly to QFB output Selects the primary reference clock Function
MPC9893
Selects automatic switch mode or manual reference clock selection Reset of alarm flags and selected reference clock Select PLL or static test mode Clock frequency selection and configuration of clock divider modes Output enable/disable and device reset Bank A clock outputs Bank B clock outputs Clock feedback output. QFB must be connected to FB for correct operation Indicates clock failure on CLK0 Indicates clock failure on CLK1 Indicates currently selected input reference clock Negative power supply Positive power supply for the PLL (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see the application section for details. Positive power supply for I/O and core
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VCC
Supply
VCC
Table 2: FUNCTION TABLE
Control Inputs PLL_EN 0 PLL enabled. The input to output frequency relationship is that according to Table 3 if the PLL is frequency locked. Manual clock switch mode. IDCS disabled. Clock failure detection and output flags ALARM0, ALARM1, CLK_IND are enabled. ALARM0, ALARM1 and CLK_IND flags are reset: ALARM0=H, ALARM1=H and CLK_IND=REF_SEL. ALARM_RST is an one-shot function. Selects CLK0 as the primary clock source PLL bypassed and IDCS disabled. The VCO output is replaced by the reference clock signal fref. The MPC9893 is in manual mode. Automatic clock switch mode. IDCS enabled. Clock failure detection and output flags ALARM0, ALARM1, CLK_IND are enabled. IDCS overrides REF_SEL on a clock failure. IDCS operation requires PLL_EN = 0. ALARM0, ALARM1 and CLK_IND active Default 0 1
MAN/A
1
ALARM_RST
1
REF_SEL FSEL[0:3] OE/MR
0 0000 0
Selects CLK1 as the secondary clock source See Following Table
Outputs enabled (active)
Outputs disabled (high impedance tristate), reset of data generators and output dividers. The MPC9893 requires reset at power-up and after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than two reference clock cycles (CLK0,1). MR/OE does not tristate the QFB output.
Outputs (ALARM0, ALARM1, CLK_IND are valid if PLL is locked) ALARM0 ALARM1 CLK_IND CLK0 failure CLK1 failure CLK0 is the reference clock CLK1 is the reference clock
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MPC9893
Freescale Semiconductor, Inc.
Table 3: CLOCK FREQUENCY CONFIGURATION
Name M8 M82 M4 M42 M3 M32 M2M M22M M2H M22H M1L M12L M1M M12M M1H M12H FSEL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSEL1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSEL2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSEL3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fREF range [MHz] 15--25 15 25 30--50 30 50 40--66.6 40 66 6 30--50 30 50 60--100 60 100 15--25 15 25 30--50 30 50 60--100 60 100 QAx Ratio fREF *8 fREF * 4 fREF * 3 fREF * 2 fREF * 2 fREF fREF fREF fQAX [MHz] 120--200 120 200 120--200 120 200 120--200 120 200 60--100 60 100 120--200 120 200 15--25 15 25 30--50 30 50 60--100.0 60 100 0 Ratio fREF * 8 fREF * 4 fREF * 4 fREF * 2 fREF * 3 fREF * 3 / 2 fREF * 2 fREF fREF * 2 fREF fREF fREF / 2 fREF fREF / 2 fREF fREF / 2 QBx fQBX[MHz] 120--200 60--100 120--200 60--100 120--200 60--100 60--100 30--50 120--200 60--100 15--25 7.5--12.5 30--50 15--25 60--100 30--50 QFB fREF fREF fREF fREF fREF fREF fREF fREF FBa 16 8 6 8 4 16 8 4
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a. FB: Internal PLL feedback divider
Table 4: GENERAL SPECIFICATIONS
Symbol VTT MM HBM CDM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 1500 200 10 4.0 Min Typ VCC / 2 Max Unit V V V V mA pF pF Per output Inputs Condition
Table 5: ABSOLUTE MAXIMUM RATINGSa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
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Table 6: DC CHARACTERISTICS (VCC = 3.3V 5%, TA = --40 to 85C)
Symbol VIH VIL VOH VOL ZOUT IIN ICC_PLL ICC VTT a. Characteristics Input high voltage Input low voltage Output High Voltage Output Low Voltage Output impedance Input Current Maximum PLL Supply Current Maximum Quiescent Supply Current Output termination voltage VCC/2 2.0 14-17 200 5.0 4.0 2.4 0.55 0.30 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V V V A mA mA V
MPC9893
Condition LVCMOS LVCMOS IOH=-24 mAa IOL= 24 mA IOL= 12 mA VIN=VCC or GND VCC_PLL Pin All VCC Pins
The MPC9893 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
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Table 7: DC CHARACTERISTICS (VCC = 2.5V 5%, TA = --40 to 85C)
Symbol VIH VIL VOH VOL ZOUT IIN ICC_PLL ICC VTT a. Characteristics Input high voltage Input low voltage Output High Voltage Output Low Voltage Output impedance Input Current Maximum PLL Supply Current Maximum Quiescent Supply Current Output termination voltage VCC/2 2.0 17-20 200 5.0 4.0 1.8 0.6 Min 1.7 Typ Max VCC + 0.3 0.7 Unit V V V V A mA mA V VIN=VCC or GND VCC_PLL Pin All VCC Pins Condition LVCMOS LVCMOS IOH=-15 mAa IOL= 15 mA
The MPC9893 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output.
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MPC9893
Freescale Semiconductor, Inc.
Table 8: AC CHARACTERISTICS (VCC = 3.3V 5% or VCC = 2.5V 5%, TA = --40 to 85C)a
Symbol fref Input Frequency Characteristics FSEL= 000x FSEL= 001x FSEL= 010x FSEL= 011x FSEL= 100x FSEL= 101x FSEL= 110x FSEL= 111x FSEL= 000x FSEL= 001x FSEL= 010x FSEL= 011x FSEL= 100x FSEL= 101x FSEL= 110x FSEL= 111x Reference Input Duty Cycle CLK0, 1 Input Rise/Fall Time Propagation Delay (static phase offset, CLKx to FB) VCC=3.3V5% and FSEL[0:2]=111 VCC=3.3V5% VCC=2.5V5% and FSEL[0:2]=111 VCC=2.5V5% Rate of period change (phase slew rate) QAx outputs QBx outputs (FSEL=xxx0) QBx outputs (FSEL=xxx1) Output-to-output Skewb (within bank) (bank-to-bank) (any output to QFB) 45 0.1 50 -60 -200 -125 -400 Min 15.0 30.0 40.0 30.0 60.0 15.0 30.0 60.0 60.0 60.0 60.0 30.0 60.0 7.5 15.0 30.0 40 Typ Max 25.0 50.0 66.6 50.0 100.0 12.5 50.0 100.0 200.0 200.0 200.0 100.0 200.0 25.0 50.0 100.0 60 1.0 +50 +100 +25 +100 150 150 300 50 100 125 55 1.0 10 10 FSEL3=0 FSEL3=1 FSEL3=0 FSEL3=1 225 425 150 250 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % ns ps ps ps ps ps/cycle Failover switch 0.8 to 2.0V PLL locked Condition PLL locked
fMAX
Maximum Output Frequency
PLL locked
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frefDC tr, tf t()
t
tsk(O)
ps ps ps % ns ns ns ps ps ps ps See applications section See applications section See applications section 0.55 to 2.4V
DCO tr, tf tPLZ, HZ tPZL, LZ tJIT(CC)
Output duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitterc
tJIT(PER)
Period Jitterc
tJIT()
I/O Phase Jitterd FB=4: FSEL[0:2]=100 or 111 FB=6: FSEL[0:2]=010 FB=8: FSEL[0:2]=001, 011, or 110 FB=16: FSEL[0:2]=000 or 101 PLL closed loop bandwidthe Maximum PLL Lock Time
RMS (1 ) RMS (1 ) RMS (1 ) RMS (1 ) FSEL=111x 0.8-4.0
40 50 55 70 10
ps ps ps ps MHz ms
BW tLOCK a. b. c. d. e.
AC characteristics apply for parallel output termination of 50 to VTT. See application section for part-to-part skew calculation. Cycle-to-cycle and period jitter depend on the VCO frequency and output configuration. See the application section on page 9. I/O jitter depends on the VCO frequency and internal PLL feedback divider FB. See application section on page 8 and 9 for more information and for the calculation for other confidence factors than 1. -3dB point of PLL transfer characteristics.
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APPLICATIONS INFORMATION
Definitions IDCS: Intelligent Dynamic Clock Switch. The IDCS monitors both primary and secondary clock signals. Upon a failure of the primary clock signal, the IDCS switches to a valid secondary clock signal and status flags are set. Reference clock signal fref: The clock signal that is selected by the IDCS or REF_SEL as the input reference to the PLL. Manual mode: The reference clock frequency is selected by REF_SEL. Automatic mode: The reference clock frequency is determined by the internal IDCS logic.
MPC9893
signal. The feedback and newly selected reference clock edge will start to slew to alignment at the next positive edge of both signals. Output runt pulses are eliminated. Reset ALARM_RST is asserted by a negative edge. It generates a one-shot reset pulse that clears both ALARMx latches and the CLK_IND latch. If both CLK0 and CLK1 are invalid or fail when ALARM_RST is asserted, both ALARMx flags will be latched after one FB signal period and CLK_IND will be latched (L) indicating CLK0 is the reference signal. While neither ALARMx flag is latched (ALARMx = H), the CLK_IND can be freely changed with REF_SEL. OE/MR: Reset the data generator and output disable. Does not reset the IDCS flags. Acquiring frequency lock at startup 1. On startup, OE/MR must be asserted to reset the output dividers. The IDCS should be disabled (MAN/A=0) during startup to select the manual mode and the primary clock. 2. The PLL will attempt to gain lock if the primary clock is present on startup. PLL lock requires the specified lock time. 3. Applying a high to low transition to ALARM_RST will clear the alarm flags. 4. Enable the IDCS (MAN/A=1) to enable to IDCS. Power Supply Filtering The MPC9893 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9893 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9893. Figure 3. illustrates a typical power supply filter scheme. The MPC9893 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 2 mA (5 mA maximum), assuming that a minimum of 2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 3. "VCC_PLL Power Supply Filter" must have a resistance of 9-10 to meet the voltage drop criteria.
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Primary clock: The input clock signal selected by REF_SEL. The primary clock may or may not be the reference clock, depending on switch mode and IDCS status. Secondary clock: The input clock signal not selected by REF_SEL Selected clock: The CLK_IND flag indicates the reference clock signal: CLK_IND = 0 indicates CLK0 is the clock reference signal, CLK_IND =1 indicates CLK1 is the reference clock signal. Clock failure: A valid clock signal that is stuck (high or low) for at least one input clock period. The primary clock and the secondary clock is monitored for failure. Valid clock signals must be within the AC and DC specification for the input reference clock. A loss of clock is detected if as well as the loss of both clocks. In the case of both clocks lost, the MPC9893 will set the alarm flags and the PLL will stall. The MPC9893 does not monitor and detect changes in the input frequency. Automatic mode and IDCS commanded clock switch
MAN/A = 1, IDCS enabled: Both primary and secondary clocks are monitored. The first clock failure is reported by its ALARMx status flag (clock failure is indicated by a logic low). The ALARMx status is flag latched and remains latched until reset by assertion of ALARM_RST.
If the clock failure occurs on the primary clock, the IDCS attempts to switch to the secondary clock. The secondary clock signal needs to be valid for a successful switch. Upon a successful switch, CLK_IND indicates the reference clock, which may now be different as that originally selected by REF_SEL. Manual mode
MAN/A = 0, IDCS disabled: PLL functions normally and both
clocks are monitored. The reference clock signal will always be the clock signal selected by REF_SEL and will be indicated by CLK_IND. Clock output transition A clock switch, either in automatic or manual mode, follows the next negative edge of the newly selected reference clock
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MPC9893
RF = 9-- 10 RF CF
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CF = 22 F
VCC
VCC_PLL 10 nF MPC9893 VCC 33...100 nF
This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter:
tSK( PP) = t (
CLKx Common
)
+ t SK(O) + tPD, LINE(FB) + t JIT(
)
xCF
-t QFB Device 1
t
()
PD,LINE(FB)
Figure 3. VCC_PLL Power Supply Filter
Any Q
Device 1
t
JIT()
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The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3. "VCC_PLL Power Supply Filter", the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9893 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9893 in zero-delay applications Nested clock trees are typical applications for the MPC9893. Designs using the MPC9893 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9893 clock driver allows for its use as a zero delay buffer. The the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero--delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or l o n g -- t e rm j i t t e r), f e e d b a c k p a t h d e l a y a n d t h e output--to--output skew error relative to the feedback output. Calculation of part-to-part skew The MPC9893 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9893 are connected together, the maximum overall timing uncertainty from the common CLK0 or CLK1 input to any output is:
t +t ()
SK(O)
QFB
Device2
t Any Q
Device 2
JIT()
t Max. skew
SK(O)
t
SK(PP)
Figure 4. Max. I/O Jitter versus frequency Due to the statistical nature of I/O jitter a rms value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 10. Table 10: Confidence Facter CF
CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999
The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from the common clock input to any MPC9893 output of -275 ps to +265 ps relative to the reference clock input CLK0/1: tSK(PP) = [-60ps...50ps] + [-125ps...125ps] + [(30ps -3)...(30ps 3)] + tPD, LINE(FB) [-275ps...265ps] + tPD, LINE(FB)
tSK(PP) =
Example configuration: fref=100 MHz, VCC=3.3V fVCO=400 MHz, FSEL[0:2]=111 The I/O (Phase) jitter of the MPC9893 depends on the internal VCO frequency and the PLL feedback divider configuration. A high internal VCO frequency and a low PLL
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feedback divider result in lower I/O jitter than the jitter limits in the AC characterisitics (table 8 on page 6). When calculating the part--to--part skew, Table 11 "Internal VCO frequency fVCO" should be used to determine the actual VCO frequency, then use Figure 5 "Max. I/O Phase Jitter versus VCO Frequency" to determine the maximum I/O jitter for the specific VCO frequency and divider configuration. In above example calculation, the internal VCO frequency of 400 MHz corresponds to a maximum I/O jitter of 30 ps (RMS). Table 11: Internal VCO frequency fVCO
MPC9893 Configuration M1H, M12H, M2H, M22H M3, M32 M1M, M12M, M2M, M22M, M4, M42 M1L, M12L, M8, M82 fVCO 4 * fref 6 * fref 8 * fref 16 * fref PLL feedback divider FB 4 6 8 16
MPC9893
Figure 7. Max. Period Jitter versus VCO Frequency Driving Transmission Lines The MPC9893 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9893 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 8. "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9893 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC9893 OUTPUT BUFFER IN
14
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Figure 5. Max. I/O Phase Jitter versus VCO Frequency The cycle--to--cycle jitter and period jitter of the MPC9893 depend on the output configuration and on the frequency of the internal VCO. Using the outputs of bank A and bank B at the same frequency (FSEL3=0) results in a lower jitter than the split output frequency configuration (FSEL3=1). The jitter also decreases with an increasing internal VCO frequency. Figures 4 to 6 represent the maximum jitter of the MPC9893.
RS = 36
ZO = 50 OutA
MPC9893 OUTPUT BUFFER IN
14
RS = 36
ZO = 50 OutB0 ZO = 50 OutB1
RS = 36
Figure 6. Max. Cycle- -Cycle Jitter versus VCO -toFrequency
Figure 8. Single versus Dual Transmission Lines
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MPC9893
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Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 10. "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9893 OUTPUT BUFFER
14
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The waveform plots in Figure 9. "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9893 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9893. The output waveform in Figure 9. "Single versus Dual Line Termination Waveforms" shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 ( 25 / (18+17+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (nS) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386
RS = 22
ZO = 50
RS = 22
ZO = 50
14 + 22 k 22 = 50 k 50 25 = 25 Figure 10. Optimized Dual Line Termination
VOLTAGE (V)
Figure 9. Single versus Dual Waveforms
MPC9893 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 11. CLK0, CLK1 MPC9893 AC test reference for Vcc = 3.3V and Vcc = 2.5V
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
VCC VCC/2 GND VCC VCC/2 GND tSK(O) The pin-- to-- pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t() CLK0, CLK1
MPC9893
VCC VCC/2 GND VCC VCC/2 GND
FB
Figure 12. Output- -output Skew tSK(O) -toVCC
Figure 13. Propagation delay (t(), static phase offset) test reference
CLK0, 1 FB
Freescale Semiconductor, Inc...
VCC/2 GND tP T0 DC = tP /T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
TJIT() = |T0 - T1 mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles
Figure 14. Output Duty Cycle (DC)
Figure 15. I/O Jitter
TN
TN+1
TJIT(CC) = |TN - TN+1 |
T0
TJIT(PER) = |TN - 1/f0 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
Figure 16. Cycle- -cycle Jitter -toVCC=3.3V 2.4 0.55 tF tR VCC=2.5V 1.8V 0.6V
Figure 17. Period Jitter
Figure 18. Output Transition Time Test Reference
TIMING SOLUTIONS
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11
MOTOROLA
MPC9893
Freescale Semiconductor, Inc.
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 932-03 ISSUE F
4X
0.200 AB T-- U Z 9 A1
48 37
A
DETAIL Y
P
1
36
T
U V
Freescale Semiconductor, Inc...
B B1
12 25
AE V1
AE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0_ 7_ 12 _REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
13
24
Z S1 S
4X
T, U, Z DETAIL Y
0.200 AC T-- U Z
AB
G
0.080 AC
AC
BASE METAL
AD M_
TOP & BOTTOM
DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA
R
GAUGE PLANE
C F D 0.080
M
E
AC T-- U Z H DETAIL AD AA W K L_
SECTION AE- AE -
MOTOROLA
For More Information On This Product, Go to: www.freescale.com
12
0.250
N
J
TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9893
Freescale Semiconductor, Inc...
TIMING SOLUTIONS
For More Information On This Product, Go to: www.freescale.com
13
MOTOROLA
MPC9893
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MOTOROLA
For More Information On This Product, Go to: www.freescale.com
14
TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9893
Freescale Semiconductor, Inc...
TIMING SOLUTIONS
For More Information On This Product, Go to: www.freescale.com
15
MOTOROLA
MPC9893
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
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MPC9893/D TIMING SOLUTIONS

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